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ds049 (v3.0) june 25, 2007 www.xilinx.com 1 product specification ? 2006, 2007 xilinx, inc. all rights reserved. all xilinx tradem arks, registered trademarks, patents, and disclaimers are as li sted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. note: this product is being discontinued. you cannot order parts in this family after may 14, 2008. xilinx recom- mends replacing XC9500XV devices with equivalent xc9500xl devices in all designs as soon as possible. rec- ommended replacements are pin compatible, however require a v cc change to 3.3v, and a recompile of the design file. in addition, there is no 1.8v i/o support, and for the 144 and 288 macrocell devices only one output bank is sup- ported. see xcn07010 for details regarding this discontinu- ation, including device replacement recomendations for the XC9500XV device family. features ? optimized for high-performance 2.5v systems - 5 ns pin-to-pin logic delays - small footprint packages including vqfps, tqfps and csps (chip scale package) - lower power operation - multi-voltage operation - fastflash technology ? advanced system features - in-system programmable - output banking (xc95144xv, xc95288xv) - superior pin-locking and routability with fast connect? ii switch matrix - extra wide 54-input function blocks - up to 90 product-terms per macrocell with individual product-term allocation - local clock inversion with three global and one product-term clocks - individual output enable per output pin with local inversion - input hysteresis on all user and boundary-scan pin inputs - bus-hold circuitry on all user pin inputs - full ieee standard 1149.1 boundary-scan (jtag) support on all devices ? four pin-compatible device densities - 36 to 288 macrocells, with 800 to 6400 usable gates ? fast concurrent programming ? slew rate control on individual outputs ? enhanced data security features ? excellent quality and reliability - 20 year data retention - esd protection exceeding 2,000v ? pin-compatible with 3.3v core xc9500xl family in common package footprints ? hot plugging capability family overview the XC9500XV family is a 2.5v cpld family targeted for high-performance, low-voltage applications in leading-edge communications and computing systems, where high device reliability and low power dissipation is important. each XC9500XV device supports in-system programming (isp) and the full ieee 1149.1 (jtag) boundary-scan, allowing superior debug and design iteration capability for small form-factor packages. the XC9500XV family is designed to work closely with the xilinx spartan?-xl and virtex? fpga families, allowing system designers to parti- tion logic optimally between fast interface circuitry and high-density general purpose logic. as shown in ta b le 1 , logic density of the XC9500XV devices ranges from 800 to 6400 usable gates with 36 to 288 registers, respectively. multiple package options and associated i/o capacity are shown in ta b l e 2 . the XC9500XV family members are fully pin-compatible, allowing easy design migration across mul- tiple density options in a given package footprint. the XC9500XV architectural features address the require- ments of in-system programmability. enhanced pin-locking capability avoids costly board rework. in-system program- ming throughout the full commercial operating range and a high programming endurance rating provide worry-free reconfigurations of system field upgrades. extended data retention supports longer and more reliable system operat- ing life. advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. each user pin is compatible with 3.3v and 2.5v inputs, and the outputs may be configured for 3.3v, 2.5v, or 1.8v operation. the XC9500XV device exhibits symmetric full 2.5v output voltage swing to allow balanced rise and fall times. architecture description each XC9500XV device is a subsystem consisting of multi- ple function blocks (fbs) and i/o blocks (iobs) fully inter- connected by the fast connect ii switch matrix. the iob 0 XC9500XV family high-performance cpld ds049 (v3.0) june 25, 2007 06 product specification r
XC9500XV family high-performance cpld 2 www.xilinx.com ds049 (v3.0) june 25, 2007 product specification r provides buffering for device inputs and outputs. each fb provides programmable logic capability with extra wide 54 inputs and 18 outputs. the fast connect ii switch matrix connects all fb outputs and input signals to the fb inputs. for each fb, up to 18 outputs (depending on package pin-count) and associated output enable signals drive directly to the iobs. see figure 1. . figure 1: XC9500XV architecture note: function block outputs (indicated by the bold lines) drive the i/o blocks directly. in-system programming controller jtag controller i/o blocks function block 1 macrocells 1 to 18 macrocells 1 to 18 macrocells 1 to 18 macrocells 1 to 18 jtag port 3 54 i/o/gts i/o/gsr i/o/gck i/o i/o i/o i/o 2 or 4 1 i/o i/o i/o i/o 3 ds049_01_041400 function block 2 54 function block 3 54 18 18 18 18 function block n 54 fast connect ii switch matrix table 1: XC9500XV device family xc9536xv xc9572xv xc95144xv xc95288xv macrocells 36 72 144 288 usable gates 800 1,600 3,200 6,400 registers 36 72 144 288 t pd (ns) 5556 t su (ns) 3.5 3.5 3.5 4
XC9500XV family high-performance cpld ds049 (v3.0) june 25, 2007 www.xilinx.com 3 product specification r function block each function block, as shown in figure 2 is comprised of 18 independent macrocells, each capable of implementing a combinatorial or registered function. the fb also receives global clock, output enable, and set/reset signals. the fb generates 18 outputs that drive the fast connect ii switch matrix. these 18 outputs and their corresponding output enable signals also drive the iob. logic within the fb is implemented using a sum-of-products representation. fifty-four inputs provide 108 true and com- plement signals into the programmable and-array to form 90 product terms. any number of these product terms, up to the 90 available, can be allocated to each macrocell by the product term allocator. t co (ns) 3.5 3.5 3.5 3.8 f system (mhz) 222 222 222 208 output banks 1 1 2 4 table 2: XC9500XV packages and user i/o pins (not including four dedicated jtag pins) (1) xc9536xv xc9572xv xc95144xv xc95288xv 44-pin vqfp 34 34 - - 100-pin tqfp - 72 81 - 144-pin csp - - 117 - 144-pin tqfp - - 117 117 208-pin pqfp - - - 168 256-pin fbga - - - 192 280-pin csp - - - 192 1. some packages available in pb-free option. see xilinx packaging for more information. table 1: XC9500XV device family xc9536xv xc9572xv xc95144xv xc95288xv
XC9500XV family high-performance cpld 4 www.xilinx.com ds049 (v3.0) june 25, 2007 product specification r macrocell each XC9500XV macrocell may be individually configured for a combinatorial or registered function. the macrocell and associated fb logic is shown in figure 3 . five direct product terms from the and-array are available for use as primary data inputs (to the or and xor gates) to implement combinatorial functions, or as control inputs including clock, clock enable, set/reset, and output enable. the product term allocator associated with each macrocell selects how the five direct terms are used. the macrocell register can be configured as a d-type or t-type flip-flop, or it may be bypassed for combinatorial operation. each register supports both asynchronous set and reset operations. during power-up, all user registers are initialized to the user-defined preload state (default to 0 if unspecified). figure 2: XC9500XV function block macrocell 18 macrocell 1 programmable and-array product term allocators from fast connect ii switch matrix ds049_02_041400 54 1 to fast connect ii switch matrix to i/o blocks out global set/reset 3 18 ptoe 18 18 global clocks
XC9500XV family high-performance cpld ds049 (v3.0) june 25, 2007 www.xilinx.com 5 product specification r figure 3: XC9500XV macrocell within function block note: see figure 8 for additional clock enable details ds049_03_041400 to fast connect ii switch matrix additional product terms (from other macrocells) global set/reset global clocks additional product terms (from other macrocells) to i/o blocks out 1 0 54 3 ptoe d/t q s r product term allocator product term set product term clock product term reset product term oe product term clock enable ec
XC9500XV family high-performance cpld 6 www.xilinx.com ds049 (v3.0) june 25, 2007 product specification r all global control signals are available to each individual macrocell, including clock, set/reset, and output enable sig- nals. as shown in figure 4 , the macrocell register clock originates from either of three global clocks or a product term clock. both true and complement polarities of the selected clock source can be used within each macrocell. a gsr input is also provided to allow user registers to be set to a user-defined state. figure 4: macrocell clock and set/reset capability d/t ec s r macrocell ds049_04_041400 i/o/gsr product term set product term clock product term reset global set/reset global clock 1 global clock 2 global clock 3 i/o/gck3 i/o/gck2 i/o/gck1
XC9500XV family high-performance cpld ds049 (v3.0) june 25, 2007 www.xilinx.com 7 product specification r product term allocator the product term allocator controls how the five direct prod- uct terms are assigned to each macrocell. for example, all five direct terms can drive the or function as shown in figure 5 . the product term allocator can re-assign other product terms within the fb to increase the logic capacity of a mac- rocell beyond five direct terms. any macrocell requiring additional product terms can access uncommitted product terms in other macrocells within the fb. up to 15 product terms can be available to a single macrocell with only a small incremental delay of t pta , as shown in figure 6 . note that the incremental delay affects only the product terms in other macrocells. the timing of the direct product terms is not changed.. figure 5: macrocell logic using direct product term product term allocator macrocell product term logic ds049_05_041400 figure 6: product term allocation with 15 product terms macrocell logic with 15 product terms product term allocator product term allocator ds049_06_041400 product term allocator
XC9500XV family high-performance cpld 8 www.xilinx.com ds049 (v3.0) june 25, 2007 product specification r the product term allocator can re-assign product terms from any macrocell within the fb by combining partial sums of products over several macrocells, as shown in figure 7 . in this example, the incremental delay is only 2 * t pta . all 90 product terms are available to any macrocell, with a maxi- mum incremental delay of 8 * t pta . figure 7: product term allocation over several macrocells macrocell logic with 18 product terms macrocell logic with 2 product terms product term allocator product term allocator ds049_07 _041400 product term allocator product term allocator
XC9500XV family high-performance cpld ds049 (v3.0) june 25, 2007 www.xilinx.com 9 product specification r the internal logic of the product term allocator is shown in figure 8 . figure 8: product term allocator logic d/t q s r from upper macrocell to upper macrocell product term set product term clock product term reset global set/reset global set/reset global clocks product term oe product term allocator to lower macrocell from lower macrocell ds049_08_041400 1 0 ce
XC9500XV family high-performance cpld 10 www.xilinx.com ds049 (v3.0) june 25, 2007 product specification r fast connect ii switch matrix the fast connect ii switch matrix connects signals to the fb inputs, as shown in figure 9 . all iob outputs (corre- sponding to user pin inputs) and all fb outputs drive the fast connect ii matrix. any of these (up to a fan-in limit of 54) may be selected to drive each fb with a uniform delay. figure 9: fast connect ii switch matrix ds049_09_041400 function block fast connect ii switch matrix (54) i/o function block i/o block 18 18 i/o block (54) i/o d/t q d/t q
XC9500XV family high-performance cpld ds049 (v3.0) june 25, 2007 www.xilinx.com 11 product specification r i/o block the i/o block (iob) interfaces between the internal logic and the device user i/o pins. each iob includes an input buffer, output driver, output enable selection multiplexer, and user programmable ground control. see figure 10 for details. figure 10: i/o block and output enable capability i/o block macrocell ds049_10_041400 product term oe ptoe switch matrix out (inversion in and-array) global oe 1 1 to other macrocells slew rate control 0 global oe 2 available in xc95144xv and xc95288xv global oe 3 global oe 4 i/o/gts1 i/o i/o/gts2 i/o/gts3 i/o/gts4 to fast connect ii user- programmable ground bus-hold
XC9500XV family high-performance cpld 12 www.xilinx.com ds049 (v3.0) june 25, 2007 product specification r the input buffer is compatible with 3.3v cmos and 2.5v cmos signals. the input buffer uses the internal 2.5v volt- age supply (v ccint ) to ensure that the input thresholds are constant and do not vary with the v ccio voltage. each input buffer provides input hysteresis (50 mv typical) to help reduce system noise for input signals with slow rise or fall edges. each output driver is designed to provide fast switching with minimal power noise. all output drivers in the device may be configured for driving either 3.3v, 2.5v, or 1.8v cmos lev- els by connecting the device output voltage supply (v ccio ) to a 3.3v, 2.5v, or 1.8v voltage supply. figure 11(a) shows how the XC9500XV device can be used in a 2.5v only sys- tem. each output driver can also be configured for slew-rate lim- ited operation. output edge rates may be slowed down to reduce system noise (with an additional time delay of t slew ) under user control. see figure 12 . the output enable may be generated from one of four options: a product term signal from the macrocell, any of the global output enable signals (gts), always ?1?, or always ?0?. there are two global output enables for devices with 72 or fewer macrocells, and four global output enables for devices with 144 or more macrocells. any selected output enable signal may be inverted locally at each pin output to provide maximum design flexibility. each iob provides user programmable ground pin capabil- ity. this allows device i/o pins to be configured as additional ground pins in order to force otherwise unused pins to a low voltage state, as well as provide for additional device grounding capability. this grounding of the pin is achieved by internal logic that forces a logic low output regardless of the internal macrocell signal, so the internal macrocell logic is unaffected by the programmable ground pin capability. each iob also provides for bus-hold circuitry that is active during valid user operation. the bus-hold feature eliminates the need to tie unused pins either high or low by holding the last known state of the input until the next input signal is present. the bus-hold circuit drives back the same state via a nominal resistance (r bh ) of 50k ohms. see figure 13 . note: the bus-hold output will drive no higher than v ccio to prevent overdriving signals when interfacing to 2.5v com- ponents. when the device is not in valid user operation, the bus-hold circuit defaults to an equivalent 50k ohm pull-up resistor in order to provide a known repeatable device state. this occurs when the device is in the erased state, in program- ming mode, in jtag intest mode, or during initial power-up. a pull-down resistor (1k ohm) may be externally added to any pin to override the default r bh resistance to force a low state during power-up or any of these other modes. figure 11: XC9500XV devices in (a) 2.5v only and (b) mixed 3.3v/2.5v/1.8v systems in out1 out2 3.3v 2.5v gnd (b) 1.8v cmos 3.3v cmos in out XC9500XV cpld XC9500XV cpld v ccint v ccio1 v ccio2 v ccint v ccio1 v ccio2 2.5v gnd (a) 2.5v 0v 2.5v 0v 3.3v 0v 3.3v 0v 2.5v 0v 1.8v 0v 3.3v 0v 2.5v cmos 2.5v 0v 2.5v cmos 2.5v cmos 3.3v cmos or 1.8v ds049_11_051702 2.5v cmos 3.3v cmos or
XC9500XV family high-performance cpld ds049 (v3.0) june 25, 2007 www.xilinx.com 13 product specification r output banking xc95288xv and xc95144xv devices are designed with a split-rail i/o structure. this permits the utilization of multiple output drive levels for systems able to operate best in that environment. the output partitioning is by function blocks (fb). with this arrangement, designers can have some sets of outputs driving to 2.5v and others set to 1.8v. naturally, it is possible to tie all rails to a single output voltage and get all outputs driving to that level. should designs be migrated from one density to another in the same package, care should be taken to remember the voltage assignments cho- sen at the outset to assure consistency ( figure 14 ). figure 12: output slew-rate control for (a) rising and (b) falling outputs time 00 1.2v standard output voltage (a) slew-rate limited time output voltage (b) standard slew-rate limited v ccio t slew t slew 1.2v ds049_12_041400 figure 13: bus-hold logic r bh i/o set to pin during valid user operation drive to v ccio level pin 0 ds049_13_041400 figure 14: split rail v cc output power connections in xc95144xv and xc95288xv devices gnds v ccints v ccio1 v ccio2 ds049_14_011501
XC9500XV family high-performance cpld 14 www.xilinx.com ds049 (v3.0) june 25, 2007 product specification r mixed voltage the i/os on each XC9500XV device are fully 3.3v tolerant even though the core power supply is 2.5v. this allows 3.3v cmos signals to connect directly to the XC9500XV inputs without damage. in addition, the 2.5v v ccint power supply can be applied before or after 2.5v signals are applied to the i/os. in mixed 3.3v/2.5v/1.8v systems, the user pins, the core power supply (v ccint ), and the output power sup- ply (v ccio ) may have power applied in any order. this makes the XC9500XV devices immune to power supply sequencing problems (see figure 11b ). xilinx proprietary esd circuitry and high impedance initial state permit hot plugging cards using XC9500XV cplds. pin-locking capability the capability to lock the user defined pin assignments dur- ing design iteration depends on the ability of the architec- ture to adapt to unexpected changes. the XC9500XV devices incorporate architectural features that enhance the ability to accept design changes while maintaining the same pinout. the XC9500XV architecture provides for superior pin-lock- ing characteristics with a combination of large number of routing switches in the fast connect ii switch matrix, a 54-wide input function block, and flexible, bidirectional product term allocation within each macrocell. these fea- tures address design changes that require adding or chang- ing internal routing, including additional signals into existing equations, or increasing equation complexity, respectively. for extensive design changes requiring higher logic capac- ity than is available in the initially chosen device, the new design may be able to fit into a larger pin-compatible device using the same pin assignments. the same board may be used with a higher density device without the expense of board rework. in-system programming one or more XC9500XV devices can be daisy chained together and programmed in-system via a standard 4-pin jtag protocol, as shown in figure 15 . in-system program- ming offers quick and efficient design iterations and elimi- nates package handling. the xilinx development system provides the programming data sequence using a xilinx download cable, a third-party jtag development system, jtag-compatible board tester, or a simple microprocessor interface that emulates the jtag instruction sequence. all i/os are set to a high-impedance state and pulled high by the bus-hold circuitry during in-system programming. if a particular signal must remain low during this time, then a pull-down resistor may be added to the pin. reliability and endurance all XC9500XV cplds provide a minimum endurance level of 1,000 in-system program/erase cycles and a minimum data retention of 20 years. each device meets all functional, performance, and data retention specifications within this endurance limit. ieee 1149.1 boundary-scan (jtag) XC9500XV devices fully support ieee 1149.1 bound- ary-scan (jtag). extest, sample/preload, bypass, usercode, intest, idcode, highz, and clamp instructions are supported in each device. additional instructions are included for in-system programming opera- tions. figure 15: in-system programming operation (a) solder device to pcb and (b) program using download cable x5902 gnd v cc (a) (b)
XC9500XV family high-performance cpld ds049 (v3.0) june 25, 2007 www.xilinx.com 15 product specification r design security XC9500XV devices incorporate advanced data security fea- tures which fully protect the programming data against unauthorized reading or inadvertent device erasure/repro- gramming. ta b l e 3 shows the four different security settings available. the read security bits can be set by the user to prevent the internal programming pattern from being read or copied. when set, they also inhibit further program operations but allow device erase. erasing the entire device is the only way to reset the read security bit. the write security bits provide added protection against accidental device erasure or reprogramming when the jtag pins are subject to noise, such as during system power-up. once set, the write-protection may be deacti- vated when the device needs to be reprogrammed with a valid pattern with a specific sequence of jtag instructions low power mode all XC9500XV devices offer a low-power mode for individ- ual macrocells or across all macrocells. this feature allows the device power to be significantly reduced. each individual macrocell may be programmed in low-power mode by the user. performance-critical parts of the application can remain in standard power mode, while other parts of the application may be programmed for low-power operation to reduce the overall power dissipa- tion. macrocells programmed for low-power mode incur additional delay (t lp ) in pin-to-pin combinatorial delay as well as register setup time. product term clock to output and product term output enable delays are unaffected by the macrocell power-setting. timing model the uniformity of the XC9500XV architecture allows a sim- plified timing model for the entire device. the basic timing model, shown in figure 16 , is valid for macrocell functions that use the direct product terms only, with standard power setting, and standard slew rate setting. ta b le 4 shows how each of the key timing parameters is affected by the product term allocator (if needed), low-power setting, and slew-lim- ited setting. the product term allocation time depends on the logic span of the macrocell function, which is defined as one less than the maximum number of allocators in the product term path. if only direct product terms are used, then the logic span is "0". the example in figure 6 shows that up to 15 product terms are available with a span of "1". in the case of figure 7 , the 18 product term function has a span of "2". detailed timing information may be derived from the full tim- ing model shown in figure 17 . the values and explanations for each parameter are given in the individual device data sheets. table 3: data security options read security default set write security default read allowed program/erase allowed read inhibited program/erase inhibited set read allowed program/erase allowed read inhibited program/erase inhibited
XC9500XV family high-performance cpld 16 www.xilinx.com ds049 (v3.0) june 25, 2007 product specification r figure 16: basic timing model combinatorial logic propagation delay = t pd (a) combinatorial logic setup time = t su t co t psu t pco clock to out time = t co (b) d/t q combinatorial logic internal system cycle time = t system ds049_16_061200 (d) d/t q combinatorial logic setup time = t psu clock to out time = t pco (c) p-term clock path d/t q table 4: timing model parameters description parameter product term allocator (1) macrocell low-power setting output slew-limited setting propagation delay t pd + t pta * s+ t lp + t slew global clock setup time t su + t pta * s+ t lp - global clock-to-output t co --+ t slew product term clock setup time t psu + t pta * s+ t lp - product term clock-to-output t pco --+ t slew internal system cycle period t system + t pta * s+ t lp - notes: 1. s = the logic span of the function, as defined in the text.
XC9500XV family high-performance cpld ds049 (v3.0) june 25, 2007 www.xilinx.com 17 product specification r power-up characteristics the XC9500XV devices are well behaved under all operat- ing conditions. during power-up each XC9500XV device employs internal circuitry which keeps the device in the qui- escent state until the v ccint supply voltage is at a safe level (approximately 1.9v). during this time, all device pins and jtag pins are disabled and all device outputs are disabled with the pins weakly pulled high, as shown in table 5 . when the supply voltage reaches a safe level, all user reg- isters become initialized (typically within 300 s), and the device is immediately available for operation, as shown in figure 18 . if the device is in the erased state (before any user pattern is programmed), the device outputs remain disabled with weak pull-up. the jtag pins are enabled to allow the device to be programmed at any time. all devices are shipped in the erased state from the factory. if the device is programmed, the device inputs and outputs take on their configured states for normal operation. the jtag pins are enabled to allow device erasure or bound- ary-scan tests at any time. figure 17: detailed timing model d/t q sr t in t logilp s*t pta t f t pdi t sui t coi t hi t aoi t rai t out t slew t en ds049_17_061200 t logi t ptck t ptsr t ptts t gck t gsr t gts macrocell ec figure 18: device behavior during power-up v ccint no power 3.8 v (typ) 0 v no power quiescent state quiescent state user operation initialization of user registers ds049_18_061200 1.9v (typ) table 5: XC9500XV device characteristics device circuitry quiescent state erased device operation valid user operation iob bus-hold pull-up pull-up bus-hold device outputs disabled disabled as configured device inputs and clocks disabled disabled as configured function block disabled disabled as configured jtag controller disabled enabled enabled
XC9500XV family high-performance cpld 18 www.xilinx.com ds049 (v3.0) june 25, 2007 product specification r power-up guidelines figure 19 shows a block diagram of the internal configura- tion controller, which transfers the eprom bits to the latches. some important things to note are: ? the v ccint is sensed to determine when to begin the loading. ? an internal clock source drives a state machine that controls the overall process. ? the bit loading process takes about 100 microseconds. ? internal configuration latches are automatically reset at the beginning of the process. ? the state machines, counters and strobes are built from cmos transistors, so they need voltage, setup time, hold time, and propagation delay time to work properly. when v ccint passes a threshold, it automatically enables. the state machine cycles through addresses, delivers load strobes to internal latches and completes the process by enabling the i/o pins. figure 20 describes what happens inside the chip as the supply rises to its final value. at low voltage, the transistors do not behave like transistors. as v cc passes about a volt, the transistors begin to wake up, but are not yet fully functional. above 1v, they can amplify and form basic gates. near 1.8v, they work correctly and can make reliable latches. above 2v, they can be reliably loaded with eprom bits. it is in this voltage neighborhood the por circuits begin transferring eprom bits to the latches. XC9500XV por begins about 1.8v. development system support the XC9500XV family and associated in-system program- ming capabilities are fully supported in either software solu- tions available from xilinx. the foundation series is an all-in-one development system containing schematic entry, hdl (vhdl, verilog, and abel), and simulation capabilities. it supports the XC9500XV family as well as other cpld and fpga fami- lies. the alliance series includes cpld and fpga implementa- tion technology as well as all necessary libraries and inter- faces for alliance partner eda solutions. the xilinx webpowered software solution offers design- ers the flexibility to target the xc9500 and coolrunner ? series cplds on the desktop with webpack. webpack downloadable desktop solutions offer free cpld software modules for abel and hdl synthesis, device fitting and jtag programming. figure 19: configuration controller clock state machine address strobes + - v ccint v por ds049_19_061200 figure 20: power-up activity 0 time v cc v por configuration completes, part comes "alive" reset pulse delivered configuration begins logic alive, latches working supply arrives at final value transistors waking up inactive silicon, slight leakage ds049_20_061200
XC9500XV family high-performance cpld ds049 (v3.0) june 25, 2007 www.xilinx.com 19 product specification r revision history the following table shows the revision history for this document. date version revision 01/19/99 1.0 initial xilinx release. advance information specification. 06/12/00 1.1 updated 3.3v information, added output banking, added ds049 number. added webpack information and minor edits. added "power-up guidelines" on page 18 . 01/15/01 2.0 new performance and package options, removed references to "fast flash". 06/24/02 2.1 updated ta b le 1 , t pd , t su , t co , and f system specs. changed to preliminary. removed references to 1.8v inputs in text and in figure 11 . 04/15/05 2.2 revised pdf attributes. no change to documentation. 01/16/06 2.3 removed pc44 and cs48 packages as per xcn05020 . 02/25/07 3.0 notice of discontinuance.

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